// ===========================================================
// FileName : tb.v
// Function : Simulation driver module (stimulus block) 
//            for the top-level block instance of Intro_Top.
//
// This module includes an initial block which assigns various
// values to top-level inputs for simulation.   
// Initial blocks are ignored in logic synthesis.
//
// ------------------------------------------------------------------
// Author   : QilinZhao
// Version  : v-1.0
// Date     : 2013-06-28
// E-mail   : forqilin@163.com
// Copyright: QiXin Studio
// ------------------------------------------------------------------
//
// `timescale 1ns/100ps   // No semicolon after `(anything)

module tb;    // Stimulus blocks have no port

  reg  Astim, Bstim, Cstim, Dstim;  // To accept initialization
  wire Xwatch, Ywatch, Zwatch;      // To connect to design instance

  // testcase 
  initial  // execution only once
  begin
    // `include "../misc/Extras.inc"
    $dumpportsall;
    $dumpfile("VCS_SimuRun.VCD"); // IEEE1364 Waveform format: vpd/fsdb
    $dumpvars;

    // Each '#' precedes a delay time, here in 1 ns units:
  
    #1  Astim = 1'b0;   // For Astim, 1 bit, representing a binary 0.
    #1  Bstim = 1'b0;
    #1  Cstim = 1'b0;
    #1  Dstim = 1'b0;
    #50 Astim = 1'b1;
    #50 Bstim = 1'b1;
    #50 Cstim = 1'b1;
    #50 Dstim = 1'b1;
    #50 Bstim = 1'b0;
    #50 Dstim = 1'b0;
    #50 Dstim = 1'b1;
    #50 Astim = 1'b0;
    #50 Cstim = 1'b0;
    #50 Dstim = 1'b0;
    #50 $finish(2);   // Terminates simulation. $finish(0|1|2);
  end // No semicolon after end.

  initial begin   // multiple-initial blocks run parallel
    $vcdpluson(); // simulator VCS dump waveform task
  end

  // The instance of the design is named Topper01, and its
  // ports are associated by name with stimulus input and simulation
  // output wires:
  
  Intro_Top Topper01 ( .X(Xwatch), 
                       .Y(Ywatch), 
                       .Z(Zwatch),
                       .A(Astim ),  
                       .B(Bstim ),  
                       .C(Cstim ), 
                       .D(Dstim )
                   );

endmodule // TestBench.
